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DEVICE FOR SUPPLYING OPERAND TO 'N+1' OPERATOR DISPOSED IN SYTSTOLIC ARCHITECTURE
DEVICE FOR SUPPLYING OPERAND TO 'N+1' OPERATOR DISPOSED IN SYTSTOLIC ARCHITECTURE
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机译:用于向符号体系结构中的“ N + 1”种运算符提供操作数的设备
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摘要
PURPOSE: To provide a device for supplying operands to 'n+1' operators disposed in a systolic architecture for reducing time necessary for processing an arithmetic sequence. ;CONSTITUTION: This device includes the preceding register AR(k) of 'n+1' designated to respectively process the sequence of the 'm+1' of the arithmetic of 'n+1', to supply operand to the operator OP (k) of 'n+1' disposed in this systolic architecture to relate with the operator and to house the operand of the first 'n+1' of arithmetic next to the arithmetic sequence of 'm+1' in the middle of present processing of the sequence of 'm+1'.;COPYRIGHT: (C)1996,JPO
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机译:目的:提供一种设备,用于将操作数提供给布置在脉动式体系结构中的“ n + 1”个运算符,以减少处理算术序列所需的时间。 ;组成:该设备包括指定为分别处理算术运算n + 1的m + 1序列的“ n + 1”寄存器AR(k),以将操作数提供给运算符OP( k)布置在此脉动式体系结构中的“ n + 1”与操作员相关联,并在当前处理过程的中间,将算术的第一个“ n + 1”的操作数紧接着“ m + 1”的算术序列'm + 1'的序列。;版权:(C)1996,日本特许厅
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