SERIAL/PARALLEL CONVERTER, PARALLEL/SERIAL CONVERTER AND ARITHMETIC PROCESSING UNIT

摘要

PURPOSE: To prevent overwrite with simple circuit configuration by connecting a 1st serial parallel S/P conversion circuit and a 3rd S/P conversion circuit or a 2nd S/P conversion circuit and the 3rd conversion circuit differentially, receiving data of a group serially and outputting the data in parallel. ;CONSTITUTION: When switches UiA (i=1-3) of a 1st group and switches U_j (j=4-9) of a 3rd group are sequentially closed by a 1st read pointer, data being components of input data IN are latched sequentially in registers RiA and R_j. Similarly the data are sequentially delayed by 1st bit unit time delay elements H1B-H3B of a 2nd group and delayed by 1st bit unit time delay elements H4-H9 by a 2nd write pointer WPB. A 1st read enable signal REA and a 2nd signal REB are applied alternately in an alternate timing. Then the signal REA or REB is applied to a switch T_j via an OR circuit ORR, then data latched in the registers R4-R9 are outputted from an output terminal OUT.;COPYRIGHT: (C)1995,JPO