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FAULT TOLERANT INTERCONNECT TOPOLOGY

机译:容错互连拓扑

摘要

An interconnect topology providing enhanced fault tolerance to a multi-component data processing system (10). The topology utilizes a plurality of rings (26-29) for interconnecting multiple system components (25a-d), or cards, at least two of which are indirectly connected so that communication therebetween is through a third component. Each of the system components (25a-d) is coupled to a set of at least two different rings (26-29) and includes interface circuits (282, 284) for routing data and a bridge (202) for permitting data to be transferred between the at least two rings (26-29).
机译:一种互连拓扑,为多组件数据处理系统(10)提供增强的容错能力。拓扑利用多个环(26-29)来互连多个系统组件(25a-d)或卡,其中至少两个间接连接,以便它们之间的通信通过第三组件进行。每个系统组件(25a-d)耦合到一组至少两个不同的环(26-29),并包括用于路由数据的接口电路(282、284)和用于允许数据传输的桥(202)在至少两个环之间(26-29)。

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