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Non-volatile progammable read only memory device having memory cells each implemented by a memory transistor and a switching transistor coupled in parallel and method of memorizing a data bit
Non-volatile progammable read only memory device having memory cells each implemented by a memory transistor and a switching transistor coupled in parallel and method of memorizing a data bit
An electrically erasable and programmable read only memory device comprises a plurality of series combinations (MB11 to MBmn) of memory cells (MC111 o MCmn3) arranged in rows and columns, bit lines (Y1 to Yn) each coupled to the front memory cells of the series combinations in one of the columns, a source line (S) coupled to the rearmost memory cells of the plurality of series combinations, and word lines (WA1 to WAm/WB1 to WBm) associated with the row of the memory cells, wherein each of the memory cells is implemented by a parallel combination of a floating gate type memory transistor (MT) and a switching transistor (ST) coupled to first and second word lines (WA1 to WAm)/WB1 to WBm), respectively, so that any memory cell is rewriteable without simultaneous erasing operation on the series combination.
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机译:一种电可擦可编程只读存储设备,包括多个按行和列排列的存储单元(MC111 o MCmn3)的串联组合(MB11至MBmn),位线(Y1至Yn),每个均耦接到存储单元的前存储单元。列之一中的串联组合,耦合到多个串联组合中的最后的存储单元的源极线(S),以及与该存储单元的行相关联的字线(WA1至WAm / WB1至WBm),其中每个通过分别耦合到第一和第二字线(WA1至WAm)/ WB1至WBm)的浮栅型存储晶体管(MT)和开关晶体管(ST)的并联组合来实现存储单元的存储单元。存储单元是可重写的,而无需在串行组合上同时进行擦除操作。
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