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Semiconductor integrated circuit having post-package testing function for error detection and correction circuit

机译:具有用于错误检测和校正电路的封装后测试功能的半导体集成电路

摘要

In a semiconductor integrated circuit including therein an electrically writable non-volatile semiconductor memory (10) and an error detection and correction circuit (3) for detecting and correcting an error of data read out from the semiconductor memory, there is provided an output selection register (6) set with a register setting signal (RS) so as to output a selection signal (R) having the level of the stored content of the output selection register itself. A selection signal switching circuit (7) receives the selection signal (R) from the output selection register (6) and another selection signal (S) from an output selection memory cell section (4) of the non-volatile semiconductor memory (10). The selection signal switching circuit (7) selects one of the received selection signals in accordance with a test signal (TS) and outputs the selected selection signal (DS) to a data selection circuit (5). With this arrangement, even after the semiconductor integrated circuit is assembled in a package or a system both of which do not allow to erase the content of the memory, it is possible to verify the operation of the error detection and correction circuit (3). IMAGE
机译:在其中包括可电写的非易失性半导体存储器(10)和用于检测和校正从半导体存储器读出的数据的错误的错误检测和校正电路(3)的半导体集成电路中,提供了输出选择寄存器。 (6)用寄存器设置信号(RS)设置,以便输出具有输出选择寄存器本身的存储内容电平的选择信号(R)。选择信号切换电路(7)从输出选择寄存器(6)接收选择信号(R),并从非易失性半导体存储器(10)的输出选择存储单元部分(4)接收另一个选择信号(S)。 。选择信号切换电路(7)根据测试信号(TS)选择接收到的选择信号之一,并将选择的选择信号(DS)输出到数据选择电路(5)。通过这种布置,即使在将半导体集成电路组装在不允许擦除存储器内容的封装或系统中之后,也可以验证错误检测和校正电路(3)的操作。 <图像>

著录项

  • 公开/公告号EP0509485B1

    专利类型

  • 公开/公告日1996-10-02

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号EP19920106532

  • 申请日1992-04-15

  • 分类号G06F11/26;

  • 国家 EP

  • 入库时间 2022-08-22 03:47:55

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