Aliasing errors in signature analysis testing of integrated circuits

摘要

The authors present an accurate model of aliasing probability in signature analysis testing, based on the assumption of independent error bits, that makes it possible to treat the statistical behavior of the register as a Markov process. A proof is given that minimum-hardware registers realizing maximal counting sequences represent optimal choices for aliasing minimization. Exact as well as simplified expressions of aliasing probability have been derived, and a criterion for the identification of maximal aliasing conditions is presented to be used as a tool for the choice of optimal test length.