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LOGICAL THREE-DIMENSIONAL INTERCONNECTIONS BETWEEN INTEGRATED CIRCUIT CHIPS USING A TWO-DIMENSIONAL MULTI-CHIP MODULE PACKAGE
LOGICAL THREE-DIMENSIONAL INTERCONNECTIONS BETWEEN INTEGRATED CIRCUIT CHIPS USING A TWO-DIMENSIONAL MULTI-CHIP MODULE PACKAGE
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机译:使用二维多芯片模块封装的集成电路芯片之间的逻辑三维互连
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摘要
A high-capacity gate array which incorporates an effectively three-dimensional interconnect network. The array is formed from multiple smaller arrays which are connected to a common substrate by means of flip-chip bonding. The substrate is typically a multi-layer substrate which has interconnect lines embedded on or within it, thereby allowing a set of desired interconnections between the smaller logic cell arrays to be implemented. The contact points for connecting logic cells or arrays of cells to the substrate result from placing a multitude of solder bumps on the smaller arrays of logic cells at desired interconnect points. Connecting the interconnect point solder bumps to the multi-layer substrate then permits the individual logic cell arrays to be interconnected in a desired manner. A three-dimensional interconnect network is realized by interconnecting corresponding points on different logic cell arrays so that the arrays are connected in parallel. This has the effect of producing a three-dimensional interconnect network from a two-dimensional arrangement of arrays or chips in an MCM package. The result is a high gate capacity logic device having an increased degree of gate utilization and shortened average interconnect distances, thereby enabling the production of complex devices which have a faster operating speed.
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