The present invention relates to a high capacity gate array incorporating an effective three-dimensional interconnect network. The array is formed from smaller multiple arrays that are connected to a common substrate by flip-flop bonding. The substrate is typically a multi-layer substrate having interconnect lines inserted on or within the substrate, allowing a preferred set of interconnections between smaller arrays of logic cells to be implemented. Contacts that connect a logic cell or an array of cells to the substrate are caused by placing a plurality of solder bumps on a smaller array of logic cells at the desired interconnection point. Then, by connecting the solder bumps of the interconnection points to the multilayer substrate, it is possible for the individual logic cell arrays to be interconnected in a preferred manner. Three-dimensional interconnection networks are realized by interconnecting corresponding points on different logical cell arrays such that the arrays are connected in parallel. This results in the formation of a three dimensional interconnection network from a two dimensional arrangement of arrays or chips in an MCM package. The result is a logic device with a maximum gate capability that allows for the fabrication of complex devices with faster operating speeds, with increased gate utilization and shortened average interconnect spacing.
展开▼
