The memory access circuit of a CD ROM decoder having an input block for converting a serial data of a DSP into a parallel data and storing it at an external memory, an error correcting block for correcting the error of the stored data and restoring it at the memory, a CPU interface unit for transmitting and receiving information to/from a system CPU, and a host interface unit for exchanging information with the CPU interface unit and transmitting the stored data to a host computer, is characterized in that the input block comprises a synchronization detecting and inserting unit for detecting a synchronization signal from the output of the DSP and if there is no synchronization, inserting the synchronization signal; a data rearranging unit for rearranging the output of the synchronization detecting and inserting unit and outputting it from a lower bit; a descrambler for descrambling the output of the data rearranging unit; a serial/parallel converter for converting the output of the descrambler into a parallel data; and a timing generator for generating a signal for controlling an operation timing of each unit.
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