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BUS ACCESS DEVICE, BUS ARBITRATION SYSTEM, CD-ROM DECODER, DVD-ROM DECODER AND CD-ROM DRIVE

机译:总线访问设备,总线仲裁系统,CD-ROM解码器,DVD-ROM解码器和CD-ROM驱动器

摘要

PROBLEM TO BE SOLVED: To provide a bus access arbitration system for a CD-ROM decoder, a DVD-ROM decoder and a CD-ROM drive, etc., which does not fix acquisition conditions of an access right such as a priority and limitation of the number of acquisitions and copes with a variety of uses. ;SOLUTION: This device has plural input-output devices 52 and 53 between which at least one has different bus use rights whose priorities do not continue and which are used for a system that shares a bus, a bus access arbitration circuit 55 which makes the use of a bus use right of input-output controllable whose priority is at least in a higher rank among bus use rights of the input- output device which has different bus use rights whose priority do not continue and a bus access count limitation circuit 51 which limits the access number of the bus access arbitration circuit. For instance, when host CPU transfer takes priority over error correction, it is possible to execute the error correction with high bus use efficiency because the error correction performs read/write by using the access margin time of the host CPU.;COPYRIGHT: (C)1999,JPO
机译:解决的问题:提供用于CD-ROM解码器,DVD-ROM解码器和CD-ROM驱动器等的总线访问仲裁系统,该系统不能确定诸如优先级和限制之类的访问权限的获取条件。的数量,并应对各种用途。 ;解决方案:该设备具有多个输入输出设备52和53,其中至少一个具有不同的总线使用权,这些总线使用权的优先级不连续,并且它们用于共享总线的系统,总线访问仲裁电路55使得总线输入仲裁器55在优先级至少不连续的输入输出设备的总线使用权中,优先级至少为较高等级的可控制的输入输出的总线使用权的使用以及总线访问次数限制电路51限制总线访问仲裁电路的访问号。例如,当主机CPU传输优先于错误校正时,由于错误校正通过使用主机CPU的访问余量时间执行读/写操作,因此可以以较高的总线使用效率执行错误校正。; COPYRIGHT:(C )1999,日本特许厅

著录项

  • 公开/公告号JPH11120124A

    专利类型

  • 公开/公告日1999-04-30

    原文格式PDF

  • 申请/专利权人 TOSHIBA CORP;

    申请/专利号JP19970296395

  • 发明设计人 SHINTANI FUMIHIKO;KOITABASHI NORIKO;

    申请日1997-10-14

  • 分类号G06F13/37;G06F3/06;G11B20/10;

  • 国家 JP

  • 入库时间 2022-08-22 02:31:58

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