Digital Clock Doubling Circuit with Stable Reset Signal Generation Circuit

摘要

The present invention relates to a circuit for doubling an input clock source using a pure digital circuit, and provides a digital clock doubling circuit capable of generating two clock cycles using one cycle of a clock to be doubling. Pulse separating means 21 for separating the pulses; First counter protection means (3); Second counter protection means (4); Reset signal generation means (13) for generating a reset signal at each edge of the clock signal and outputting a load signal inverting the reset signal; First up counting means (5); Second up counting means (6); First dispensing means (7); Second dispensing means (8); Multiplexing means (11); First inverting means (9); First logical product calculating means (10); And a down counting means 12 which toggles the trigger signal at the end point of the half cycle after the trigger signal is obtained and outputs the one-to-one semiconductor.