A semiconductor device includes spaced-apart, surface-adjoining, laterally-oriented first and second device regions. A channel region at least partially surrounds the second device region, and a gate region is provided adjacent to, but insulated from, the second device region and the channel region. The gate region extends in a substantially vertical direction adjacent the second device region and the channel region in order to induce a substantially vertical conduction channel in the channel region of the device during operation. The gate region can advantageously be provided in a trench surrounding the transistor device, with a trench-shaped gate dielectric layer being provided on the trench sidewalls and floor to insulate the gate from the remainder of the device. Devices may be fabricated in an epitaxial surface layer, which may be provided either directly on a semiconductor substrate, or else on an intervening insulating layer. These devices provide the advantages of low on-resistance, fast switching speed, high breakdown voltage and high latch up current density. IMAGE
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