Pseudo-NMOS logic circuits with negligible static current during quiescent current testing

摘要

A modified pseudo-nMOS logic gate for use in systems in which quiescent current testing is desired. The load transistor of each pseudo- nMOS gate is controlled by a two-input load control gate. One input of the load control gate is connected to a global test signal and the second input of the load control gate is connected to the output of the pseudo- nMOS gate. In normal operation, the global test signal is logically true, and the load control gate has no effect on the pseudo-nMOS gate. During quiescent current testing, the global test signal is logically false and the output of the load control gate is determined by the logical output of the pseudo-nMOS gate. If the output of the pseudo-nMOS gate is logically true, the load control gate has no effect on the pseudo-nMOS gate. If the output of the pseudo-nMOS gate is logically false, the load control gate turns off the load transistor so that no static current flows through the load transistor. As a result, the logical state of the pseudo-nMOS gate is preserved, but the modified gate draws negligible static current during quiescent current testing.