Test vector generator comprising a decompression control unit and a conditional vector processing unit and method for generating a test vector

摘要

An apparatus for testing an electronic device, in particular an integrated circuit tester and specifically designed for testing memories or logic/memory combinations, provides a multiplicity of pin channels. Each pin channel includes a sequence controller communicating with a decompression control unit. This combination is extremely fast and allows to designate the respective pin channels to an address or a data pin of a memory or to a logic pin of a device under test. A central controller provides the necessary control instructions to instruction memories of the sequence controllers. All sequence controllers assigned to a logic pin execute basically the same program, wherein pin adaptation is performed by a vector memory. In contrast, sequencers assigned to an address pin execute different, pin-specific instructions. The architecture may be easily adapted to varying pin definitions and is based on the "per pin resource" approach. It may also be applied to board testers and other electronic testing devices.