TEST VECTOR GENERATOR, TEST VECTOR GENERATING METHOD, FAILURE ANALYZER FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND PROGRAM FOR GENERATING TEST VECTOR

摘要

PROBLEM TO BE SOLVED: To provide a test vector generator for generating a test vector used to test a specific domain by naming the specific domain in a semiconductor integrated circuit.;SOLUTION: Retrieval conditions are named for selecting a path allowing a signal to be transmitted therethrough in the semiconductor integrated circuit. Timing analysis is executed based on circuit information on the integrated circuit, a path is retrieved satisfying the retrieval conditions, and a path list is prepared in which cells constituting the retrieved path are put in the order of execution of timing analysis. Based on the path list, a test vector is generated for testing path delay failure of the integrated circuit. A termination condition is named for terminating the generation of the test vector. The preparation of the path list is terminated when the termination condition is satisfied.;COPYRIGHT: (C)2004,JPO