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Ultra high speed data collection, processing and distribution ring with parallel data paths between nodes

机译:节点之间具有并行数据路径的超高速数据收集,处理和分发环

摘要

A high speed data collection processing and distribution system for coupling a plurality of digital data sources to a plurality of digital data processors. The system includes a plurality of segmented parallel data paths and a plurality of nodes connecting said parallel data paths in an endless ring. Each node includes an input connector for connecting the end of one of said segments of parallel data paths on a one-for-one basis; a data multiplexer, a plurality of node parallel data paths in the node corresponding to the segmented parallel data paths, respectively, connected to the input connector and the data multiplexer such that data input to the multiplexer corresponds to respective ones of the segmented parallel data paths. A processor is coupled to said node parallel data paths, and as a second input to the multiplexer a common source of clock and slot signals is independently connected to said control processor in each node, respectively, for controlling the timing thereof. Each node also includes transmit and receive FIFO buffer memories, address, exclusive source and pattern match circuits and a local clock distribution circuit.
机译:一种高速数据收集处理和分配系统,用于将多个数字数据源耦合到多个数字数据处理器。该系统包括多个分段的并行数据路径和在环形环中连接所述并行数据路径的多个节点。每个节点包括一个输入连接器,用于一对一地连接并行数据路径的所述段之一的末端。数据多路复用器,在节点中分别与分段并行数据路径相对应的多个节点并行数据路径连接到输入连接器和数据多路复用器,使得输入到多路复用器的数据对应于分段并行数据路径中的相应数据。处理器耦合到所述节点并行数据路径,并且作为多路复用器的第二输入,时钟和时隙信号的公共源分别独立地连接到每个节点中的所述控制处理器,以控制其时序。每个节点还包括发送和接收FIFO缓冲存储器,地址,专用源和模式匹配电路以及本地时钟分配电路。

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