Integrated circuit memory having a self-timed write pulse independent of clock frequency and duty cycle

摘要

An integrated circuit memory (20) has a write pulse generator (38) for generating a self-timed write pulse independent of system clock frequency and system clock duty cycle. The write pulse generator (38) includes a delay element (56) and a delay element (68). The write pulse is triggered on a rising edge of the clock signal and has a duration that is determined by a delay time provided by the delay element (68). The delay elements (56, 68) provide single-sided delays and compensate for process, power supply, temperature variations of the integrated circuit memory (20) .