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Heterojunction FET having barrier layer consisting of two layers between channel and buffer layers
Heterojunction FET having barrier layer consisting of two layers between channel and buffer layers
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机译:异质结FET,其势垒层由沟道层和缓冲层之间的两层组成
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摘要
A heterojunction FET disclosed herein includes a semi- insulating GaAs substrate, a buffer layer composed of an undoped In.sub. y/2 Al.sub.1-y/2 As layer (0 y 1), and having a film thickness less than or equal to a critical film thickness, a first barrier layer composed of an undoped AlAs layer and an undoped In.sub.y Al.sub.1-y As layer (0 y 1), a channel layer composed of an undoped In.sub.y Ga.sub.1-y As layer (0 y 1), a second barrier layer composed of an N-type In. sub.y Al.sub.1-y As layer (0 y 1), each layer disposed in the order mentioned, on the semi-insulating GaAs substrate, a gate electrode which is selectively disposed on the second barrier layer to form a Schottky junction, and electrodes for a drain and a source, each of which is disposed on the second barrier layer via a contact layer, with said gate electrode therebetween.
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机译:本文所公开的异质结FET包括半绝缘GaAs衬底,由未掺杂的In.sub组成的缓冲层。 y / 2 Al1-sub / 2 As层(0 展开▼