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FAILURE ANALYSIS OF SEMICONDUCTOR WAFER AND DEVICE THEREOF

机译:半导体晶片的故障分析及其装置

摘要

PROBLEM TO BE SOLVED: To make it possible to accurately grasp a pattern defect generation process. ;SOLUTION: When a pattern defect 1 is detected in an (n-2)th process, pattern defects in an (n-1)th process are retrieved, all the pattern defects detected in the (n-1)th process at a prescribed region, where the pattern defect 1 is detected, are decided to be ones generated in the (n-2)th process and when pattern defects 2 and 3 are detected outside of the prescribed region, these pattern defects 2 and 3 are decided to be ones developed in the (n-1)th process. Then, pattern defects in an nth process are retrieved, all the pattern defects detected in the nth process at a prescribed region, where the defects 2 and 3 are detected in the (n-1)th process, are decided to be ones generated in the (n-1)th process and when pattern defects 4, 5 and 6 are detected outside of the prescribed region, where the defects 2 and 3 are detected, these defects 4, 5 and 6 are decided to be ones developed in the nth process.;COPYRIGHT: (C)1997,JPO
机译:要解决的问题:为了能够准确地掌握图案缺陷的产生过程。 ;解决方案:当在第(n-2)个过程中检测到图案缺陷1时,将检索第(n-1)个过程中的图案缺陷,在第(n-1)个过程中检测到的所有图案缺陷都将在将检测到图案缺陷1的指定区域确定为在第(n-2)个处理中生成的区域,并且当在指定区域之外检测到图案缺陷2和3时,将这些图案缺陷2和3确定为是在第(n-1)个过程中开发的。然后,取回第n个工序中的图案缺陷,将在第n-1个工序中检测出缺陷2和3的规定区域的,在第n个工序中检测出的所有图案缺陷判定为在第n个工序中产生的图案缺陷。在第(n-1)工序中,在检测出缺陷2和3的规定区域以外检测出图案缺陷4、5、6的情况下,判定为在第n次显影的缺陷4、5、6。版权:(C)1997,日本特许厅

著录项

  • 公开/公告号JPH09134940A

    专利类型

  • 公开/公告日1997-05-20

    原文格式PDF

  • 申请/专利权人 MATSUSHITA ELECTRIC IND CO LTD;

    申请/专利号JP19960172251

  • 发明设计人 HAGI TOSHIO;NAKADA KAZUKI;

    申请日1996-07-02

  • 分类号H01L21/66;G01R31/26;G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-22 03:35:27

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