Analog multiplier using an octotail cell or a quadritail cell

摘要

A multiplier in which simplification of a circuit configuration and reduction of a current consumption can be realized. There are provided with first, second, third and fourth pairs of transistors whose capacities are the same as each other and these four pairs are driven by a single constant current source. A sum of first and second input voltage is applied in positive phase to an input end of the first pair and the sum is applied in opposite phase to the other input end thereof. A difference of the first and second input voltages is applied in positive phase to an input end of the second pair and the difference is applied in opposite phase to the other input end thereof. Input ends of the third pair and those of the fourth pair are coupled together to be applied with a direct current voltage. The output ends coupled of the first pair and those coupled of the third pair are coupled together to form one differential output end, and the output ends coupled of the second pair and those coupled of the fourth pair are coupled together to form another differential output end. IMAGE