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How to shorten TTA (Turn Around Time) in manufacturing custom semiconductors

机译:在定制半导体的制造中如何缩短TTA(周转时间)

摘要

The present invention relates to a method for shortening the TAT (Turn Around Time) in manufacturing a semiconductor, and to provide a method for shortening the TAT (Turn Around Time) which can cope with a short delivery time requirement of a user and is suitable for cost reduction of a user. .;The TAT (Turn Around Time) shortening method of the present invention for separating the field region and the active region on the semiconductor substrate to grow a field oxide film in the field region, forming a gate electrode and a cap insulating film on the active region Implanting low concentration n impurity ions for source / drain formation using the gate electrode as a mask, forming a gate sidewall in the resultant, and implanting high concentration n + impurity ions to form a source / drain region in the semiconductor substrate on both sides of the gate electrode Forming a planarization insulating film on the resultant and selectively removing the planarization insulating film to form contact holes of all combinations in a cell part to be used and a cell part not to be used, the cell part to be used Forming a metal pattern for electrical connection to the cell site, The portion where the contact hole is formed is characterized by forming a dummy metal pattern that is not electrically connected to cover the contact hole forming portion.
机译:本发明涉及一种缩短半导体制造中的TAT(周转时间)的方法,并且提供一种能够缩短TAT(周转时间)的方法,该方法可以应对用户的短交货时间要求并且是合适的。用于降低用户成本。本发明的TAT(周转时间)缩短方法用于分离半导体衬底上的场区和有源区,以在场区中生长场氧化膜,在其上形成栅电极和盖绝缘膜。有源区注入低浓度n -杂质离子,以栅电极为掩模形成源极/漏极,在所得物中形成栅侧壁,并注入高浓度n + 杂质离子在栅电极两侧的半导体衬底中形成源/漏区,在所得物上形成平坦化绝缘膜,并选择性地去除平坦化绝缘膜,以在要使用的单元部分中形成所有组合的接触孔;以及不使用的电池部分,使用的电池部分形成用于与电池位置电连接的金属图案,形成接触孔的部分的特征在于,形成虚设金属不电连接以覆盖接触孔形成部分的图案。

著录项

  • 公开/公告号KR960043041A

    专利类型

  • 公开/公告日1996-12-21

    原文格式PDF

  • 申请/专利权人 문정환;

    申请/专利号KR19950010688

  • 发明设计人 최민수;

    申请日1995-05-01

  • 分类号H01L21/328;

  • 国家 KR

  • 入库时间 2022-08-22 03:18:51

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