首页> 外国专利> OPENNING DEVICE OF AIR HOLE IN THE CABINET OF CONSUMER ELECTRONICS

OPENNING DEVICE OF AIR HOLE IN THE CABINET OF CONSUMER ELECTRONICS

机译:消费电子柜中的气孔开放装置

摘要

The line memory controller of a camcoder is comprised of: an address controller (11) deciding a capacity of 1/2 line memories (15 and 16) to output a start/stop signals in accordance with it; a counter (12) generating an address signal (ADD) at a half rate of a main clock signal (CK) under a control of the address controller (11), and outputting 1/2 clock signal (1/2CK); a delay element (13) delaying the 1/2 clock signal (1/2CK) output from the address counter (12) by one clock on the basis of the main clock signal (CK) to output it; a delay element (14) delaying the address signal (ADD) output from the address counter (12) by one clock on the basis of the main clock signal (CK) to output it; an 1/2 line memory (15) directly provided with the address signal (ADD) output from the address counter (12), and provided with the 1/2 clock signal (1/2CK) output from least significant bit (LSB) of the counter (12) as a read enable signal(RE1) and a write enable signal (WE1) to read/write image data of one horizontal line every one period of the main clock signal (CK); an 1/2 line memory (16) directly provided with the address signal (ADD) output from the delay element (13), and provided with the 1/2 clock signal (1/2CK) output from the delay element (14) as a read enable signal(RE2) and a write enable signal (WE2) to read/write image data of one horizontal line to alternate with the read/write operation of the 1/2 line memory (15) every one period of the main clock signal (CK).
机译:凸轮编码器的行存储器控制器包括:地址控制器(11),其决定1/2行存储器(15和16)的容量以根据其输出启动/停止信号;计数器(12)在地址控制器(11)的控制下以主时钟信号(CK)的一半的速率产生地址信号(ADD),并输出1/2时钟信号(1 / 2CK);延迟元件(13)基于主时钟信号(CK)将地址计数器(12)输出的1/2时钟信号(1 / 2CK)延迟一个时钟,以将其输出;延迟元件(14)基于主时钟信号(CK)将从地址计数器(12)输出的地址信号(ADD)延迟一个时钟,以输出该延迟信号;一个1/2行存储器(15),直接提供从地址计数器(12)输出的地址信号(ADD),并提供从该地址的最低有效位(LSB)输出的1/2时钟信号(1 / 2CK)计数器(12)作为读使能信号(RE1)和写使能信号(WE1),以每一个主时钟信号(CK)的周期读/写一条水平线的图像数据; 1/2行存储器(16)直接提供有从延迟元件(13)输出的地址信号(ADD),并具有从延迟元件(14)输出的1/2时钟信号(1 / 2CK),作为读取使能信号(RE2)和写入使能信号(WE2),以在主时钟的每个周期交替读取/写入一条水平线的图像数据,以与1/2行存储器(15)的读取/写入操作交替进行信号(CK)。

著录项

  • 公开/公告号KR970001234Y1

    专利类型

  • 公开/公告日1997-02-21

    原文格式PDF

  • 申请/专利权人 구자홍;

    申请/专利号KR19930028832U

  • 发明设计人 신동권;

    申请日1993-12-21

  • 分类号H05K7/20;

  • 国家 KR

  • 入库时间 2022-08-22 03:18:43

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号