Fabrication of Single-Electron Transistor Operating at Room Temperature Using Low-voltage Vacuum Deposition of Scanning Penetrating Microscope

摘要

The present invention relates to a method of fabricating a room temperature working single electron transistor using low voltage vacuum deposition of a scanning tunneling microscope.;More particularly, the present invention relates to a method of forming a tunnel structure by forming an island and a tunneling junction on a silicon oxide film using low voltage vacuum deposition of scanning tunneling microscopy (STM) To a method of manufacturing a single electron transistor (SET).;The method of manufacturing a room temperature operating SET of the present invention is a method of manufacturing a room temperature operating SET in which a gold tip 2 serving as a probe of STM approaches a silicon oxide film 1 on a silicon substrate 10 in a vacuum environment, Maintaining the tip at a distance of 4 to 6 angstroms; An electric pulse of 5 to 10 V is applied between the silicon oxide film 1 and the gold tip 2 to form a continuous low voltage vacuum deposition process in which gold atoms forming the gold tip 2 are vacuum deposited on the surface of the silicon oxide film 1 Dimensional island structure 3 of a few nanometers in size and a source 5 and a drain 6 are formed at left and right sides of the island structure 3 so as to be spaced apart from each other by a predetermined distance, Forming a vacuum electron-penetrating barrier (4); And bonding the gate 7 to the opposite surface of the silicon substrate 10 described above.;According to the manufacturing method of the present invention, since the size of the island structure of the SET is easily formed in the nanometer size, the SET that can be operated at room temperature can be economically manufactured, so that the realization of the low power and highly integrated circuit can be accelerated.