Electrostatic discharge (ESD) protection circuit and structure for output drivers

摘要

An integrated circuit device includes internal power supply buses V. sub.SSI, and V.sub.DDI, and output power supply buses V.sub.SSO, and V. sub.DDO. An output driver of the device has an active p-channel pull up, and n-channel pulldown complementary pair configuration with their outputs tied to a common node, which is in turn tied to an I/O pad. A protection circuit for protecting the device from ESD events includes a series resistor disposed between the source of the n-channel pulldown transistor, and power supply bus V.sub.SSO. The protection circuitry includes a diode having its cathode connected to the I/O pad, and its anode connected to power supply bus V.sub.SSI. The pulldown transistor includes an n.sup.+ drain region, which is shared with the diode, wherein the diode and transistor are merged. The resistor between the pulldown transistor source, and power supply V.sub.SSO permits maintaining this merged structure. In an alternate embodiment, an n-well may be formed to underlie the p.sup.+ anode of the diode, and wholly surround it. The n- well extends toward and contacts the n.sup.+ drain region of the pulldown FET. The n-well isolates the p.sup.+ region from the substrate, permitting the p.sup.+ region to be connected to the power supply bus V. sub.SSO thereby eliminating the requirement that a metal power supply bus V.sub.SSI be routed into the I/O portion of the device.