Main memory system for fault tolerant computer amp; system and protocol for checkpoint

摘要

(57) Abstract Without constraining the normal operation of the computer the mechanism which maintains a state where it possesses the coherence in main memory is offered, as for the computer & the system, it becomes possible with that, to recover from fault without losing the continuity of the data or treatment. In the typical computer & the system, the processor and the input/output element, through the memory bus, it is jointed to main memory. It is jointed also the shadow storage element and to this memory bus which include with buffer memory and the main memory element. Is desired (therefore, in the midst of running are all applications which after the fault safely returning it can do checkpoint, in main memory it possesses coherence a state where it is established,) when, the data which is captured first in buffer memory, is copied to the main memory element of the shadow storage element. This structure and protocol, a state where it possesses the coherence in main memory is guaranteed, fault tolerant operation is made possible.