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SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR MEMORY CIRCUIT TO BE TESTED, TESTING METHOD OF SEMICONDUCTOR MEMORY CIRCUIT AND READOUT CIRCUIT OF SEMICONDUCTOR AND READOUT CIRCUIT FOR SEMICONDUCTOR MEMORY CIRCUIT
SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR MEMORY CIRCUIT TO BE TESTED, TESTING METHOD OF SEMICONDUCTOR MEMORY CIRCUIT AND READOUT CIRCUIT OF SEMICONDUCTOR AND READOUT CIRCUIT FOR SEMICONDUCTOR MEMORY CIRCUIT
PROBLEM TO BE SOLVED: To locate the faulty spots generated in the memory section of a semiconductor memory circuit and to reduce the time required for testing. SOLUTION: In a semiconductor device 100 provided with a semiconductor memory circuit 103 the behaviour of which is tested in combination with an external testing means 101, the semiconductor device 100 is provided with a test pattern generator 102 which generates the test pattern showing the type of the test in response to the command from the testing means 101 and the expectation expected to be obtained from the test pattern, a semiconductor memory circuit 103 provided with plural memory cells which are arranged in the form of a matrix of rows and columns and respectively store data and operates based on the test patterns to output the data of each memory cell for each row, a judging means 104 which compares the output data from the circuit 103 with its expectation to output the results of comparison and a converter section 105 which converts the results of comparison to output to an external test means 101.
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