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Semiconductor equipment, insulating gate die field-effect transistor and Schottky gate die field-effect transistor

机译:半导体设备,绝缘栅模场效应晶体管和肖特基栅模场效应晶体管

摘要

PURPOSE:To control the occupation factor of carriers at an interface level by a method wherein a Dirac delta doped layer is formed on a compound semiconductor layer making its base reach the depth equal to a debye length or less from the surface of the semiconductor layer. CONSTITUTION:An n-type GaAs layer 12 is epitaxially grown on a semi- insulating GaAs substrate 11 through an MBE method so as to have a specified thickness, and then Si is epitaxially grown thereon in a single atomic layer to form a delta doped layer 13. Then, an n-type GaAs layer is epitaxially grown again on the delta doped layer 13 to make the n-type GaAs layer 12 as thick as specified. And, an AuGe/Ni film is formed on the whole face, which is patterned through etching and then subjected to a heat treatment to make the AuGe/Ni film and the n-type GaAs layer 12 alloyed for the formation of a source 16 and a drain 17. Then, an insulating film is formed on the whole face, which is patterned through etching to form a gate insulating film 14. Next, a metal film of Al or Au is formed on the whole face, which is patterned through etching for the formation of a gate electrode 15. By this set-up, the occupation factor of carriers at an interface level can be controlled.
机译:目的:通过一种方法在载流子的界面水平上控制载流子的占有率,其中在化合物半导体层上形成狄拉克δ掺杂层,使它的基底距半导体层表面的深度等于或小于德拜长度。构成:通过MBE法在半绝缘GaAs衬底11上外延生长n型GaAs层12,使其具有规定的厚度,然后在单原子层中外延生长Si,形成δ掺杂层。 13.然后,在δ掺杂层13上再次外延生长n型GaAs层,以使n型GaAs层12达到指定的厚度。并且,在整个表面上形成AuGe / Ni膜,通过蚀刻对该AuGe / Ni膜进行构图,然后进行热处理,以使AuGe / Ni膜和n型GaAs层12合金化以形成源极16和N。漏极17。然后,在整个表面上形成绝缘膜,该绝缘膜通过蚀刻被图案化以形成栅极绝缘膜14。接着,在整个表面上形成Al或Au的金属膜,其通过蚀刻被图案化。通过该设置,可以控制在界面水平上的载流子的占有率。

著录项

  • 公开/公告号JP2770340B2

    专利类型

  • 公开/公告日1998-07-02

    原文格式PDF

  • 申请/专利权人 SONII KK;

    申请/专利号JP19880223097

  • 申请日1988-09-06

  • 分类号H01L29/78;H01L21/338;H01L29/778;H01L29/812;

  • 国家 JP

  • 入库时间 2022-08-22 03:00:57

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