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Method and system for controlling a cache

机译:控制缓存的方法和系统

摘要

A cache controller is coupled between a central processing unit (CPU) and a memory management unit (MMU). The MMU is coupled to main memory, and the cache controller is further coupled to a cache memory. A cache controller transfers a block of N programming instructions from the main memory into the cache memory. Once this transfer is complete, the CPU begins the sequential execution of the N instructions. Generally concurrently, the cache controller scans each of the N instructions to detect branch instructions. Branch instructions are those instructions which require additional data not found within the block of N instructions previously loaded into the cache. Upon detection a branch instruction, and prior to the execution of the branch instruction by the CPU, the cache controller fetches the branch instruction data from main memory, and stores it within the cache.
机译:高速缓存控制器耦合在中央处理单元(CPU)和内存管理单元(MMU)之间。 MMU耦合到主存储器,并且高速缓存控制器还耦合到高速缓存存储器。缓存控制器将N条编程指令的块从主存储器传输到缓存中。传输完成后,CPU开始顺序执行N条指令。通常并发地,高速缓存控制器扫描N条指令中的每条指令以检测分支指令。分支指令是那些需要附加数据的指令,这些附加数据在先前装入高速缓存的N条指令的块中找不到。在检测到分支指令时,并且在由CPU执行分支指令之前,高速缓存器控制器从主存储器获取分支指令数据,并将其存储在高速缓存器中。

著录项

  • 公开/公告号EP0488567B1

    专利类型

  • 公开/公告日1998-05-06

    原文格式PDF

  • 申请/专利权人 SUN MICROSYSTEMS INC;

    申请/专利号EP19910310653

  • 发明设计人 SHERMIS HERSCHEL J.;

    申请日1991-11-19

  • 分类号G06F9/38;

  • 国家 EP

  • 入库时间 2022-08-22 02:50:44

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