The arrangement includes a phase-/frequency regulation arrangement (3) which is supplied with the data signal stream, and a frequency divider arrangement (13) which is controlled by a data word (DW). The frequency divider arrangement is arranged in the feedback branch of the phase-/frequency regulation arrangement, and provides a clock signal (T) at its output. A bit rate recognition arrangement (15) is supplied with the data signal stream and at least one reference frequency signal, and produces the bit-rate dependent data word (DW) supplied to the frequency divider arrangement. The bit-rate recognition arrangement is preferably supplied with at least two reference frequency signals.
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