BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission circuit, and in particular, to add a means for delaying a clock for a predetermined time programmatically to an integrated circuit that receives data, to prevent a malfunction by matching the timing between the transmission data and the clock. In the present invention, the integrated circuit 220 for receiving data from the integrated circuit 210 includes a buffer 221 for receiving transmission data and a flip-flop for latching the output data of the buffer 221 and transmitting the latched data to the internal circuit. 223, a buffer 222 for supplying the clock CK2 to the flip-flop 223, and a delayed clock CK1 to the buffer 222 by delaying the clock CLK by a predetermined time according to the selection signal SEL. It is configured to include a clock delay unit 224 to apply.
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