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Semiconductor component e.g. silicon carbide MOS transistor for smart power integrated circuit

机译:半导体元件用于智能功率集成电路的碳化硅MOS晶体管

摘要

In known high voltage smart-power integrated circuits, the power semiconductor component often takes up more than half of the entire chip surface. In order to produce integrated circuits more cost effectively, the consumption of material, especially the drift zone surfaces of power semiconductor components, clearly need to be reduced. Silicon carbide contains an approximately electric breakdown field strength which is ten times higher than that of silicon. The integration of parts of a semiconductor component which receive voltage with silicon carbide enables the production of considerably smaller drift zones which have identical blocking voltage. In a lateral current conducting SiC-MOS-transistor, the SiC layer (6) which is approximately between 1-2 mu m thick and covered by a SiO2 layer (11) is arranged on a Si-substrate (2) in a dielectrically isolated manner. Two respective n+-doped SiC areas (7,8) serve as source contacts or drain contacts. The electron conducting channel is formed on the surface of a p+-doped area (13) of the SiC layer (6) situated opposite from the gate electrode (14). Said area (13) is connected to the only weak electron conducting SiC drift zone (12).
机译:在已知的高压智能功率集成电路中,功率半导体组件通常占据整个芯片表面的一半以上。为了更有效地生产集成电路,显然需要减少材料的消耗,尤其是功率半导体组件的漂移区表面。碳化硅的击穿电场强度大约是硅的十倍。半导体元件的接收电压与碳化硅的部分的集成使得能够产生具有相同阻断电压的相当小的漂移区。在横向导电的SiC-MOS晶体管中,大约1-2μm厚并且被SiO 2层(11)覆盖的SiC层(6)被电绝缘地布置在Si衬底(2)上。方式。两个相应的n +掺杂的SiC区域(7,8)用作源极触点或漏极触点。电子传导通道形成在SiC层(6)的与栅电极(14)相对的p +掺杂区(13)的表面上。所述区域(13)连接到唯一的弱电子传导SiC漂移区(12)。

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