首页> 外国专利> MOS field effect transistor with improved pocket regions for suppressing any short channel effects and method for fabricating the same

MOS field effect transistor with improved pocket regions for suppressing any short channel effects and method for fabricating the same

机译:具有改进的口袋区域以抑制任何短沟道效应的MOS场效应晶体管及其制造方法

摘要

A method for ion-implantation of a first conductivity impurity into a substrate of the same conductivity type to form pocket regions at positions in the inside edge portion of source/drain regions of a second conductivity type in a MOSFET having gate electrodes with side wall silicon oxide films. Semiconductor epitaxial layers are formed on the source/drain regions of a high selectivity to the side wall oxide films so that the epitaxial layers have facets which face to the side wall oxide films and the facets are almost linearly sloped down to bottom portions of the side wall oxide films. The first conductivity type impurity is implanted into the substrate at its limited positions in the vicinity of the inside edge portion of the source/drain regions by using the epitaxial layers with the facets and the side wall oxide films as masks in an oblique direction tilted by a tilting angle &thgr; from the normal of a surface of the substrate, wherein the angle &thgr; satisfies an equation represented by &thgr;≦&thgr;.sub.1 where:&thgr;.sub. 1 is an angle by which the facets are tilted from the normal of the surface substrate, and a thickness of the silicon selective growth layers satisfies an equation Tepi (Xj'/tan &thgr;)-Xj where: Tepi is the thickness of the silicon selective growth layers except for the facet portions; Xj is a junction depth of the source/drain diffusion regions; and Xj' is a distance between a top edge portion of each of the source/drain diffusion regions and a bottom side edge of each of the side wall oxide films.
机译:在具有栅硅和侧壁硅的MOSFET中,将第一导电杂质离子注入到相同导电类型的衬底中以在第二导电类型的源/漏区的内边缘部分的位置处形成袋状区域的方法氧化膜。在对侧壁氧化膜具有高选择性的源/漏区上形成半导体外延层,使得外延层具有面向侧壁氧化膜的小平面,并且小平面几乎线性地向下倾斜到侧面的底部。壁氧化膜。通过使用以小平面和侧壁氧化膜为倾斜方向倾斜的外延层作为掩模,在源/漏区的内边缘部分附近的有限位置处将第一导电型杂质注入到衬底中。倾斜角&thgr;从基板表面的法线开始,其中角度θ满足由&thgr;≦&thgr; .sub.1表示的方程式,其中: 1是小平面从表面基板的法线倾斜的角度,并且硅选择性生长层的厚度满足方程Tepi>(Xj'/ tan&thgr;)-Xj,其中:Tepi是表面的厚度。除刻面部分之外的硅选择性生长层; Xj是源/漏扩散区的结深度; Xj′是每个源/漏扩散区的顶边缘部分和每个侧壁氧化膜的底侧边缘之间的距离。

著录项

  • 公开/公告号US5733792A

    专利类型

  • 公开/公告日1998-03-31

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号US19960688266

  • 发明设计人 SADAAKI MASUOKA;

    申请日1996-07-29

  • 分类号H01L21/266;

  • 国家 US

  • 入库时间 2022-08-22 02:39:53

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号