CMOS limited-voltage-swing clock driver for reduced power driving high- frequency clocks

摘要

A buffer or driver circuit drives a high-capacitance clock signal line inside an integrated circuit (IC). Power is reduced by limiting the voltage swing of the clock output. The clock voltage swing is limited to within a transistor threshold-voltage of power and ground by feeding the output voltage back to the gates of the driver transistors which drive the output clock signal line. Thus the output clock swings from Vtn to Vcc-|Vtp| rather than from ground to Vcc. The limited output swing reduces dynamic power which is more critical than static power in downstream logic receiving the clock for higher-speed clocks. Crowbar current from power to ground through the driver transistors is eliminated by turning off the active driver transistor before the complementary driver is turned on. The gates of the driver transistors are charged and discharged from the clock line capacitance rather than from power and ground. This sequencing is accomplished by a delay in switching feedback transistors after the gate of the active driver transistor is tied to power or ground by a tie-off transistor. Bleeder transistors may be added to the clock output to reduce static power if the clock may be stopped or slowed down.