Space saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memory

摘要

A space saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memory. The method and floor plan allow for a significant reduction in the physical area required for a buffer memory of any given size that is fabricated on integrated circuit. Buffer applications wherein random access to the buffered data is not required use a CMOS dynamic serial memory with p- channel devices supplied with a voltage less positive than the voltage supplied to their respective n-wells. In a particular embodiment, three memory stages are used in a cascaded fashion. The first and third memory stages store data on a parallel basis, while the second memory stage stores data on a serial basis. The second memory stage call be fabricated using much less chip area per bit than the first and third memory stages. Significant area reduction is achieved because the second memory stage eliminates addressing overhead associated with conventional high-density memory schemes, and low voltage power supplies permit relaxation of latch- up prevention layout rules.