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LOGARITHMIC AMPLIFIER CIRCUIT WITH AMPLIFYING AND RECTIFYING CIRCUITS

机译:对数放大器电路,带有放大和整流电路

摘要

PROBLEM TO BE SOLVED: To obtain a logarithmic amplifier circuit which is suitably realizes on a semiconductor circuit and with a low temperature dependence of the logarithmic characteristic of an output signal. SOLUTION: Each of amplifying and rectifying circuits S1 to Sn is constituted of a MOS differential pair 4 consisting of MOS transistors M1 and M2, and a triple tail cell 5 consisting of MOS transistors M5 to M7 and a constant current source 1. MOS transistors M3 and M4 are provided as the loads of the differential pair 4, and MOS transistors M8 and M9 are provided as the loads of the cell 5. The gates of the MOS transistors M5 and M6 form an input terminal, while the drains of M5 and M6 form an amplifying output terminal and the drain of M7 forms a rectifying output terminal.
机译:要解决的问题:获得一种对数放大器电路,该对数放大器电路适合在半导体电路上实现并且对输出信号的对数特性具有较低的温度依赖性。解决方案:每个放大和整流电路S1至Sn由一个由MOS晶体管M1和M2组成的MOS差分对4和一个由MOS晶体管M5至M7和恒流源1组成的三尾单元5组成。MOS晶体管M3提供M1和M4作为差分对4的负载,并且提供MOS晶体管M8和M9作为单元5的负载。MOS晶体管M5和M6的栅极形成输入端子,而M5和M6的漏极形成输入端子。形成放大输出端子,M7的漏极形成整流输出端子。

著录项

  • 公开/公告号JPH11251853A

    专利类型

  • 公开/公告日1999-09-17

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP19980054039

  • 发明设计人 KIMURA KATSUHARU;

    申请日1998-03-05

  • 分类号H03G11/08;H03F1/30;H03F3/45;H03G3/10;

  • 国家 JP

  • 入库时间 2022-08-22 02:37:17

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