DESIGN METHOD OF VLSI CHIP

摘要

PROBLEM TO BE SOLVED: To provide a VLSI(Very Large Scale Integrated Circuit) chip design method, wherein an LVPC(logic vs. physical check) and a DRC(design rule check) are applied to a chip mounted with a large number of circuits and component elements, and disadvantages of a physical design can be reduced to zero. SOLUTION: A chip is divided into three segments 3 to be subjected to a DRC and an LVPC. Consequerntly, memory requirements are kept below the limit of a platform used for verification, and necessary times can be reduced shapely. This method includes a first step where a chip region is divided into a few segments 3, a second step where the segments 3 are physically cut off by introducing divider macro into the boundaries 11 between the segments 3, and a third step where circuits are arranged on the segments 3, so as to enable a usable check device to deal with the circuits related to the segments 3.