首页> 外国专利> Design method for VLSI chips arranged on a carrier and module thus designed

Design method for VLSI chips arranged on a carrier and module thus designed

机译:用于布置在载体上的超大规模集成电路芯片的设计方法和由此设计的模块

摘要

A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.
机译:描述了用于布置在载体(3)上的VLSI芯片(1,2)的系统设计以及由此设计的模块。在自上而下的设计系统中,通过同步设计芯片和芯片载体,以同步方式同时优化电路。整体逻辑分为适合芯片的分区。考虑最小的总连接长度并优选地提供并联连接,将芯片放置在载体上。输入/输出触点(121至221、131至231、141至241)在对应时彼此相对分配在芯片上。它们由平行线连接。从分配的I / O触点开始,从外部到内部完成了几个芯片的设计。总的来说,通过结合最佳的总体设计和最佳的芯片设计,提供了一种高成品率和高性能的半导体薄膜硅多芯片模块。作为从一开始就包括在设计中的载体(3),优选地使用薄膜无源硅载体。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号