LOGIC CIRCUIT VERIFICATION DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND LOGIC CIRCUIT VERIFICATION METHOD FOR LOGIC CIRCUIT VERIFICATION DEVICE

摘要

PROBLEM TO BE SOLVED: To reduce the number of events that occur without changing the logic of a circuit and to accelerate logical circuit verification by converting circuit connection information of an extracted asynchronous circuit into circuit connection information of a synchronous circuit, based on circuit conversion information that has been read from a circuit information library. SOLUTION: First, a synchronous circuit extracting part 2 outputs a synchronous circuit and an asynchronous circuit which are divided by a program 1 of HDL description to a logical gate expanding part 3. The part 3 decides whether or not the asynchronous circuit is registered on a circuit information library 4, in order to convert the divided asynchronous circuit into a synchronous circuit. When it has been registered, the asynchronous circuit is replaced by a synchronous circuit that is logically equivalent. When a desired delay value stays in a verifying circuit, the synchronous circuit that is inputted from the part 2 and the replaced synchronous circuit are outputted, and a cycle base simulation/static timing verifying part 11 performs verification.