Logic circuit verification device, logic circuit verification method and logic circuit verification program

摘要

PROBLEM TO BE SOLVED: To reduce man-hours needed for operation verification, in the design of a logic circuit wherein a signal having an irregular pattern is set as input.;SOLUTION: This logic circuit verification device includes: a test bench generation means generating a test bench configured to extract the kind of an input event and an output signal in a strobe point in the strobe point depending on the input event; a simulation means acquiring a first result that is a result obtained by executing simulation in operation verification-completed timing to a prescribed signal of the test bench generated by the test bench generation means, and a second result that is a result obtained by making input timing of the prescribed input signal be swept in prescribed timing to execute the simulation; and a result decision means comparing the kinds of the input event in the first result and the second result, and the logical value of the output signal to decide truth/falseness of operation of the logic circuit.;COPYRIGHT: (C)2012,JPO&INPIT