A method of manufacturing a multi-level semiconductor device, which method comprises: forming a first dielectric layer (40) on a semiconductor substrate; forming a first patterned metal layer (41a-41d) having gaps therein on the first dielectric layer (40), depositing a high density plasma oxide (42) to fill the gaps by high density plasma chemical vapor deposition; performing a first heat treatment at a first temperature for a first period of time to substantially increase the grain size of the first patterned metal layer (41a-41d), performing a second heat treatment at a second temperature lower than the first temperature, for a second period of time shorter than the first period of time. Application to borderless vias.
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