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A method of manufacturing a field emission array (FEA) on a silicon (SOI) substrate formed on an insulating layer

机译:一种在绝缘层上形成的硅(SOI)衬底上制造场发射阵列(FEA)的方法

摘要

The present invention relates to a method of fabricating a FEA integrated with an FEA for FED and / or MOSFET by applying LOCOS technology on an SOI substrate, comprising the steps of: doping a monocrystalline silicon layer on an SOI substrate; 11. A method of manufacturing a semiconductor device, comprising: forming a buffer oxide film (12) by high temperature thermal oxidation of a silicon oxide film (11) on a substrate; forming a silicon nitride film (13) on the buffer oxide film; Etching a buffer oxide film in a portion where there is no silicon nitride film strip pattern and etching the exposed doped silicon layer; forming a fine silicon nitride film pattern (132) on the silicon nitride film strip pattern; Forming a gate oxide film 14 by etching the silicon nitride film pattern; wet etching the silicon nitride film pattern to etch the buffer oxide film located below Forming a gate hole (15) by encapsulating the exposed silicon layer; forming a gate electrode (15) by vertically depositing an evaporation material on the silicon substrate to form a gate electrode layer (16) Forming a metal layer in the hole, and forming a field emission tip (17) on the metal layer in the gate hole.
机译:本发明涉及通过在SOI衬底上应用LOCOS技术来制造与用于FED和/或MOSFET的FEA集成的FEA的方法,该方法包括以下步骤:在SOI衬底上掺杂单晶硅层;以及在SOI衬底上掺杂单晶硅层。 11.一种制造半导体器件的方法,包括:通过在基板上高温氧化氧化硅膜(11)形成缓冲氧化膜(12);在缓冲氧化膜上形成氮化硅膜(13);在没有氮化硅膜条图案的部分中蚀刻缓冲氧化膜并蚀刻暴露的掺杂硅层;在氮化硅膜条图案上形成精细的氮化硅膜图案(132);通过蚀刻氮化硅膜图案形成栅氧化膜14;湿蚀刻氮化硅膜图案以蚀刻位于下方的缓冲氧化膜,通过密封暴露的硅层形成栅孔(15);通过在硅衬底上垂直沉积蒸发材料以形成栅电极层(16)来形成栅电极(15),从而在孔中形成金属层,并在栅中的金属层上形成场发射尖端(17)孔。

著录项

  • 公开/公告号KR19990024672A

    专利类型

  • 公开/公告日1999-04-06

    原文格式PDF

  • 申请/专利权人 하제준;이종덕;

    申请/专利号KR19970045945

  • 发明设计人 우형수;이종덕;이천규;

    申请日1997-09-05

  • 分类号H01L29/76;

  • 国家 KR

  • 入库时间 2022-08-22 02:17:30

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