Device isolation structure and method in semiconductor power integrated circuit

摘要

The present invention relates to a device isolation structure and a method thereof in a semiconductor power integrated circuit, and the device isolation structure includes a semiconductor substrate having a high voltage device region and a low voltage device region defined therein; A trench formed in the high voltage device region of the semiconductor substrate in an interfacing region of the high voltage device and the low voltage device; A fourth insulating film, a fifth insulating film, and a conductive film sequentially buried in the trench; A first insulating film pattern formed on the semiconductor substrate including the trench; And a field insulating film formed on the semiconductor substrate exposed between the insulating film patterns on the top surface of the trench. When the field insulating film is formed by the LOCOS method, oxygen permeates into the void space formed in the conductive film of the trench, It is possible to suppress the occurrence of breakdown between high-voltage devices even at a high voltage, thereby improving process reproducibility, process cost, and process reliability.