SEMICONDUCTOR RANDOM ACCESS MEMORY CELL ON SILICON-ON-INSULATOR WITH DUAL CONTROL GATES

摘要

An object of the present invention is a stacked gate memory cell of a memory cell array configured on a SOI substrate to adjust the potential of the floating channel by varying the voltage of the second control gate and the second control gate embedded directly below the conducting channel of the cell. A memory cell in which a selected cell is programmed or erased without disturbing adjacent cells by means of FN tunneling through the floating gate and channel after a particular cell is selected, including a first control gate, the word line deposited on the floating gate. It is to provide a stacked gate memory cell of the array. The second control gate can be used for reading information stored in the floating gate and also for preventing disturbances. The second control gate is parallel to the bit line and perpendicular to the word line first control gate. The floating gate and the cell are located at the intersection of the first control gate and the second control gate. Thus, the cell can be programmed or erased through FN tunneling by only changing the voltages of the first and second control gates.