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Dynamic random access memory-semiconductor memory device, has two memory cells with gates, where gates are switchable by control switching device at beginning of preloading process for loading bit lines to compensation voltage
Dynamic random access memory-semiconductor memory device, has two memory cells with gates, where gates are switchable by control switching device at beginning of preloading process for loading bit lines to compensation voltage
The device has memory cells (2) with a selection transistor, where gates of the transistor are connected to word lines. A pair of bit lines is connected to a sense amplifier, and two memory cells (6) are connected to the bit lines. A control switching device (7`) is provided, where gates of the memory cells (6) are switchable by the device (7`) at the beginning of a preloading process for loading the bit lines to a compensation voltage. An independent claim is also included for a method for increasing readability of a dynamic random access memory-memory cell in a memory cell field.
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