Binary Convolution Adder Circuit of Multipliers

摘要

The present invention relates to a binary convolution adder circuit of a multiplier for quickly processing a subtotal generated by processing a partial term of a multiplier using a full adder and a half adder. Input the sum of FA (1-1 to 1-5) and FA (1-1 to 1-3) to output carry and FA (2-1) to output sum and carry, FA (1-4, 1) Input of the sum of the -5) and the last bit of input FA (2-2) to output the sum and the carry, and FA (2- to output the sum and the carry by inputting the carry of the FA (1-1 to 1-3) 3) Input the carry of FA (1-4, 1-5) to output the sum and carry and input the sum of HA (2-4) and FA (2-1, 2-2) to input the final sum and carry HA (3-1), FA (2-3) and HA (2-4) outputting the sum and carry by inputting the carry of HA (3-1) and FA (2-1, 2-2). Input the sum of) to output the sum and carry and input the carry of HA (3-3), FA (2-3) and HA (2-4) to output the sum and carry. FA (4-1), HA (3-2, which outputs C1 and carry by inputting the sum of the carry of HA (3-4), HA (3-1) and HA (3-2, 3-3) Input the sum of carry (3-3) and HA (3-4) to output the sum and carry, and input the sum of carry (FA-2) and FA (4-2) of FA (4-1) HA (5) for outputting C2 and carry, HA (3-4) FA (4-2) and input for carry of HA (5) and FA (6) for outputting the sum of C3 and the carry of C4. .