A display device for controlling an input voltage of the phase locked loop circuit in accordance with an input display mode

摘要

The present invention relates to a display device, and is provided between a microcomputer for receiving horizontal and vertical synchronizing signals and an analog video signal provided from a host to discriminate a display mode supported by a host and a PLL circuit for generating a pixel clock, And a voltage control circuit for controlling the supply of a stable voltage to the charge pump circuit in the PLL circuit for course control and a switching circuit for switching to supply a stable voltage in course control. The microcomputer uses a pixel clock output from the PLL circuit to control the frequency of the clock for analog sampling of the analog digital converter and the fine control to adjust the phase of the clock for the analog sampling of the analog digital converter At the same time, the charge pump circuit is prevented from being excited. Therefore, when the DC voltage is applied to the charge pump circuit, the division frequency of the divider is changed so that the PLL circuit is out of the lock range, thereby preventing the loop feedback from being interrupted.