A single macroinstruction is received, which specifies at least two logical registers. These registers each store first and second operands in packed data form with data elements in mutual correspondence. An operation specified from the individual macroinstructions, is executed on numbers of first and second mutually-corresponding data elements of the first and second operands, at different times, using the same circuit to produce independently, numbers of first and second resulting data elements. These are stored in a single logical register as third packed data operands. An Independent claim is included for the corresponding processor and system.
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