Optimized, combined leading zeros counter and shifter

摘要

By combining a count leading zero circuit with a bit shifter in a digital processor though detection of groups of leading zeros prior to completion of counting of leading zeros, shifting for normalization and number format conversion can concurrently be initiated and partially carried out prior to completion of a determination of the number of leading zeros in an expression of a number. The combined count leading zero circuit and shifter provides faster operation which can be completed within one cycle time and hardware architecture simplifications are achieved to reduce required circuit element count and chip space.