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COMBINED LEADING ONE AND LEADING ZERO ANTICIPATOR
COMBINED LEADING ONE AND LEADING ZERO ANTICIPATOR
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机译:领先的一头和零领先的组合
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摘要
PURPOSE: An LOA(Leading One Anticipator) coupled with an LZA(Leading Zero Anticipator) is provided to present a circuit for calculating binary numbers, recognizing and counting the leading ones and leading zeros in the numbers. CONSTITUTION: A multiplier(14) in a mantissa part(10) multiplies normalized binary numbers(A,B) by each other. A sorter(18) sorts the bits of a binary number(C). An XOR gate(20) makes a complement of the sorted number(C) in response to a signal(21). Adders(22,23) adds the multiplication result of the numbers(A,B) to the complement of the sorted number(C). The output of an adder(23) is applied to a normalizer(24). An LOA/LZA(28) performs a logical operation in order to indicate a leading one or zero of the result from the adder(22). The output of the LOA/LZA(28) is applied to a multiplexor(30). A post-normalization count logic circuit(32) converts a count signal from the LOA/LZA(28) to a shift signal for a post-normalizer(24). If a normalized number has a negative sign, an increment part(38) adds one to the normalized number, and thereby completes two's complement conversion. The part(38) may be used for a rounding operation. The post-normalizer(24) is implemented by a simple shifter.
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机译:目的:提供一个LOA(领先的一个预期者)和一个LZA(领先的零预期者),以提出一种计算二进制数,识别和计数数字中的前导和零的电路。组成:尾数部分(10)中的乘法器(14)相互乘以归一化的二进制数(A,B)。分类器(18)对二进制数(C)的位进行分类。 XOR门(20)响应于信号(21)对已排序的数字(C)进行补码。加法器(22,23)将数字(A,B)的相乘结果加到已排序数字(C)的补数上。加法器(23)的输出被施加到归一化器(24)。 LOA / LZA(28)执行逻辑运算以指示来自加法器(22)的结果的前导一或零。 LOA / LZA(28)的输出被施加到多路复用器(30)。后归一化计数逻辑电路(32)将来自LOA / LZA(28)的计数信号转换为用于后归一化器(24)的移位信号。如果归一化的数具有负号,则增量部分(38)将归一化的数加1,从而完成二进制的补码转换。零件(38)可用于修整操作。后归一化器(24)由一个简单的移位器实现。
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