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Combined leading one and leading zero anticipator

机译:前导零和前导零组合

摘要

A floating point unit (FPU) is described which processes normalized binary numbers. All multiply, add, and subtract calculations are performed using the format (A*B)+C or (A*B)-C. The operation A*B is performed in parallel with the alignment of C to the product of A*B. An output of the multiplier and the aligned operand C are applied to a carry save adder, whose output is then applied to a carry propagate adder to generate the result A*B.+-.C. The output of the carry save adder is also applied to a combined leading one anticipator (LOA) and leading zero anticipator (LZA). The output of the carry propogate adder is provided to a post normalizer. The output of the combined LOA/LZA is applied to the input of a multiplexer, with the control input of the multiplexer being connected to the most significant bit of the adder output, where this most significant bit indicates whether the result is positive or negative. The output of the multiplexer will thus reflect the leading zero count, if the output of the adder is a positive number, or the leading one count, if the output of the adder is a negative number. The resulting count is then used to normalize the result of A*B.+ -.C.
机译:描述了一个浮点单元(FPU),它处理归一化的二进制数。所有的乘法,加法和减法运算都是使用(A * B)+ C或(A * B)-C格式执行的。操作A * B与C与A * B乘积的对齐并行执行。乘法器的输出和对齐的操作数C应用于进位保存加法器,然后将其输出应用于进位传播加法器以生成结果A * B。+-。C。进位保存加法器的输出还应用于组合的前导一预期值(LOA)和前导零预期值(LZA)。进位推进器加法器的输出提供给后置标准化器。组合的LOA / LZA的输出被施加到多路复用器的输入,多路复用器的控制输入连接到加法器输出的最高有效位,其中最高有效位指示结果是正还是负。因此,如果加法器的输出为正数,则多路复用器的输出将反映前导零计数;如果加法器的输出为负数,则多路复用器的输出将反映前导1计数。然后将所得的计数用于归一化A * B. + -.C的结果。

著录项

  • 公开/公告号US5993051A

    专利类型

  • 公开/公告日1999-11-30

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号US19960746880

  • 发明设计人 SHAO-KUN JIANG;TED NGUYEN;

    申请日1996-11-18

  • 分类号G06F7/38;

  • 国家 US

  • 入库时间 2022-08-22 01:38:57

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